(Please accept our apology if you receive multiple copies of this CFP) ---------------------------------------------------------------------- CALL FOR PAPERS

NetEval 2009 - The First Workshop on Performance Evaluation of Next-Generation Networks

April 26, 2009 Boston, MA, USA http://cans.uml.edu/neteval2009.html

Co-located with IEEE ISPASS'09 http://www.ispass.org/ispass2009/

The design and prototyping of the next-generation Internet has been an active research area in the networking community. Significant efforts have been devoted to revise many aspects of current network design including network architecture, network protocols, security and privacy, and service abstractions. The development of experimental network testbeds (e.g. PlanetLab, Emulab, GENI, etc.) has allowed researchers to evaluate and verify innovative designs through realistic experiments at a global scale.

The design of the next-generation Internet also draws a great deal of interest from the computer architecture research community. The introduction of virtualization and programmability in router systems requires high performance embedded processing elements. Network processors, FPGAs, and multi-core processors play important roles in modern routers and switches.

The expanding functionality of the next-generation Internet and the increasing complexity of its router systems pose a novel challenge for performance evaluation. Researchers and developers involved in designing and implementing new network architectures, router systems, and network applications need the ability to thoroughly evaluate and quantitatively compare the performance of these systems. Currently, there are no established evaluation methodologies, benchmark network topologies, or application workloads to guide the performance evaluation process in next-generation networks.

The goal of this workshop is to bring together researchers and practitioners from the networking, computer architecture, and performance evaluation communities to describe, discuss, and advance the state of the art in performance evaluation of next-generation networks. The workshop solicits papers that cover analytic, simulation-based, and measurement-based performance evaluation topics in this area. Since this workshop focuses on next-generation networks, we envision that papers relate to either

1. performance evaluation techniques in next-generation networks or

2. specific performance evaluation studies of next-generation networks and their systems.

*** Topics ***

Topics of interest include, but are not limited to the following:

* Performance evaluation techniques for next-generation networks. * Active and passive measurement in next-generation networks. * Design and prototypes of network measurement systems and tools. * Performance metrics, analysis, and optimization for next- generation networks. * Performance evaluation of network processing systems based on network processors, FPGAs, or multi-core processors. * Performance studies of high performance and programmable routers * Benchmarks of next-generation network applications * Performance techniques and studies related to network virtualization. * Performance techniques and studies related to network security. * Performance techniques and studies related to cross-layer optimization. * Performance evaluation related to GENI and other next- generation network testbeds. * Prototypes and techniques for network trace collection and analysis in next-generation networks

*** Submission Instructions ***

The workshop welcomes original papers from academia and industry on work related to the above topics. Position papers are welcome and should be identified as such in the title. Submissions must not exceed 6 pages in length, must follow the IEEE conference paper formatting guidelines for US letter page size (http://www.ieee.org/web/publications/pubservices/confpub/AuthorTools/confer enceTemplates.html), and must be submitted as PDF file. Submissions that do not follow these guidelines may be rejected without consideration. Authors of accepted papers are expected to present their papers at the workshop. Submissions must be original work not under review at any other workshop, conference, or journal. Papers can be submitted through the EDAS submission site at http:// www.edas.info/newPaper.php?c=7336& .

*** Important Dates ***

Abstract submissions due Friday, Feb 27, 2009

Paper submissions due Friday, Mar 6, 2009

Notification of acceptance Monday, Mar 30, 2009

Camera ready version due Friday, Apr 10, 2009

Workshop date Sunday, Apr 26, 2009

*** Workshop Organizers ***

Yan Luo, UMass Lowell Tilman Wolf, UMass Amherst

*** Program Committee ***

Paul Barford, University of Wisconsin-Madison Laxmi Bhuyan, UC Riverside Mark Crovella, Boston University James Griffioen, University of Kentucky Yu Gu, NEC Laboratories America Gianluca Iannacone, Intel Research Berkeley Raj Jain, Washington University in St. Louis Srihari Makineni, Intel Corporation Ning Weng, Southern Illinois University at Carbondale Li Zhao, Intel Corporation

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Yan Luo, Ph.D. Assistant Professor Univ. of Massachusetts Lowell Dept. of Electrical and Computer Engineering Tel: (978) 934-2592 Fax: (978) 934-3027 Web: http://cans.uml.edu/~yluo/

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