Hallo Frau Kielhorn und Frau Schweda,

ausserhalb des Akademischen Eiffelturm-Turms, zum Beispiel hier bei uns in der Wirtschaft, werden auch noch andere Text-Systeme als "Word" eingesetzt und hier ist Ihre nette Einladung nur mit recht viel Export/Umwandeln/Import-Aufwand lesbar.

Damit meine Kolleginnen und Kollegen in der Industrie den Hassel nicht selber duchfuehren muessen (wenn das Attachment nicht ohnehin schon von ihrer Konzern-Firewall entsorgt worden war -- Hallo Volkswagen!), haenge ich hier gleich eine fuer _alle_ lesbare Text-Version an, die mir mir mein Sekretaer freundlicherweise erstellt hat.

Dr. Bhandarkar kommt ja nicht gerade von "um die Ecke" -- da es waere doch schade, wenn Huette peinlich unbesucht bleibt, nur weil die Ankuendigung unnoetigerweise exklusiv fuer Leute PCs und einem Word darauf lesbar ist. Und das, wo sich dieser Vortrag ausgerechnet mit solchen Systemen befasst, auf denen ein Word eher *nicht* verwendet wird. Wie gesagt: sowas gibt es wirklich, es ist nur manchmal ein gut gehuetetes Betriebgeheimnis.

Mit freundlichem Gruss, Martin Neitzel

Technische Universität Braunschweig Institute für Informatik

Einladung zum Kolloquium

Zeit: Mittwoch 05.05.2004; 14:15 Uhr Ort: Aula Pockelsstr, 11 <-- **** ACHTUNG!

Vortragender: Dr. Dileep Bhandarkar

Thema: Billion Transistor Microprocessor Chips in Mainstream Enterprise Platforms of the Future

Zusammenfassung

Today's leading edge microprocessors like the Intel's Itanium(TM) 2 Processor feature over 220 million transistors in 0.18e-6 m semiconductor process technology. Nanotechnology that continue to drive Moore's Law provide a doubling of the transistor density every two years. This indicates that a Billion transistor chip is possible in the 65 nm technology within the next 3 to 4 years. Such chips can be used in mainstream enterprise server platforms. Key trends in high end microprocessor design including multi-threading and multi-core will be covered. We have started to see "SMP-on-a-chip" designs for high-end enterprise servers where two processors with Level 2 (L2) cache are incorporated on a single chip. Future microprocessors will offer higher levels of multiprocessor capability on chip as the transistor density increases. Computer manufacturers are incorporating these high-end microprocessors into large symmetric multiprocessing systems with 8, 16, 32 or even 64 processors. Another trend is the emergence of clustered commercially off the shelf (COTS) servers as credible supercomputing platforms. This talk will cover anticipated advances in semiconductor technology and relate those to trends in microprocessor design that will drive higher levels of parallelism in mainstream server platforms. Several possible ways of utilizing a billion transistors will be discussed along with accompanying design challenges.

Dr. Dileep Bhandarkar is an IEEE Fellow, and a Distinguished Alumnus of the Indian Institute of Technology, Bombay, where he received his B. Tech in Electrical Engineering. He also has a M.S. and Ph.D. in Electrical Engineering from Carnegie Mellon University, and has done graduate work in Business Administration at the University of Dallas. He is currently Architect at Large in Intel's Enterprise Platforms Group. His previous positions have included Director of the Enterprise Architecture Lab, and Director of Strategic Planning for Intel Architecture processors and chipsets Prior to joining Intel in 1975, he spent almost 18 years at Digital Equipment Corporation, where he managed processor and system architecture, and performance analysis work related to the VAX, Prism, MIPS, and Alpha architectures. He also worked at Texas Instruments for 4 years in their research labs in a variety of areas including magnetic bubble memories, charge coupled devices, fault tolerant memories, and computer architecture. Dr. Bhandarkar holds 15 U.S. Patents and has published more than 30 technical papers in variousjournals and conference proceedings. He is also the author of a book titled Alpha Architecture and Implementations.